/**
 * \file IfxDom_bf.h
 * \brief
 * \copyright Copyright (c) 2019 Infineon Technologies AG. All rights reserved.
 *
 *
 * Version: TC36XA_UM_V1.2.0.R0
 * Specification: TC3xx User Manual.V1.2.0
 * MAY BE CHANGED BY USER [yes/no]: No
 *
 *                                 IMPORTANT NOTICE
 *
 *
 * Use of this file is subject to the terms of use agreed between (i) you or 
 * the company in which ordinary course of business you are acting and (ii) 
 * Infineon Technologies AG or its licensees. If and as long as no such 
 * terms of use are agreed, use of this file is subject to following:


 * Boost Software License - Version 1.0 - August 17th, 2003

 * Permission is hereby granted, free of charge, to any person or 
 * organization obtaining a copy of the software and accompanying 
 * documentation covered by this license (the "Software") to use, reproduce,
 * display, distribute, execute, and transmit the Software, and to prepare
 * derivative works of the Software, and to permit third-parties to whom the 
 * Software is furnished to do so, all subject to the following:

 * The copyright notices in the Software and this entire statement, including
 * the above license grant, this restriction and the following disclaimer, must
 * be included in all copies of the Software, in whole or in part, and all
 * derivative works of the Software, unless such copies or derivative works are
 * solely in the form of machine-executable object code generated by a source
 * language processor.

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
 * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE 
 * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * \defgroup IfxSfr_Dom_Registers_BitfieldsMask Bitfields mask and offset
 * \ingroup IfxSfr_Dom_Registers
 * 
 */
#ifndef IFXDOM_BF_H
#define IFXDOM_BF_H 1

/******************************************************************************/

/******************************************************************************/

/** \addtogroup IfxSfr_Dom_Registers_BitfieldsMask
 * \{  */
/** \brief Length for Ifx_DOM_SCICTRL_PECON_Bits.PEEN */
#define IFX_DOM_SCICTRL_PECON_PEEN_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PECON_Bits.PEEN */
#define IFX_DOM_SCICTRL_PECON_PEEN_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PECON_Bits.PEEN */
#define IFX_DOM_SCICTRL_PECON_PEEN_OFF (0u)

/** \brief Length for Ifx_DOM_SCICTRL_PECON_Bits.SETPE */
#define IFX_DOM_SCICTRL_PECON_SETPE_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PECON_Bits.SETPE */
#define IFX_DOM_SCICTRL_PECON_SETPE_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PECON_Bits.SETPE */
#define IFX_DOM_SCICTRL_PECON_SETPE_OFF (2u)

/** \brief Length for Ifx_DOM_SCICTRL_PECON_Bits.PEACK */
#define IFX_DOM_SCICTRL_PECON_PEACK_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PECON_Bits.PEACK */
#define IFX_DOM_SCICTRL_PECON_PEACK_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PECON_Bits.PEACK */
#define IFX_DOM_SCICTRL_PECON_PEACK_OFF (4u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI0_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI0_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI0_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI0_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI0_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI0_P_OFF (0u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI1_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI1_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI1_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI1_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI1_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI1_P_OFF (1u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI2_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI2_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI2_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI2_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI2_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI2_P_OFF (2u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI3_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI3_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI3_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI3_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI3_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI3_P_OFF (3u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI4_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI4_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI4_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI4_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI4_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI4_P_OFF (4u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI5_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI5_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI5_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI5_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI5_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI5_P_OFF (5u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI6_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI6_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI6_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI6_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI6_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI6_P_OFF (6u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI7_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI7_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI7_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI7_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI7_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI7_P_OFF (7u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI8_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI8_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI8_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI8_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI8_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI8_P_OFF (8u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI9_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI9_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI9_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI9_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI9_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI9_P_OFF (9u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI10_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI10_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI10_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI10_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI10_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI10_P_OFF (10u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI11_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI11_P_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI11_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI11_P_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.MCI11_P */
#define IFX_DOM_SCICTRL_PRIORITY_MCI11_P_OFF (11u)

/** \brief Length for Ifx_DOM_SCICTRL_PRIORITY_Bits.HPRS */
#define IFX_DOM_SCICTRL_PRIORITY_HPRS_LEN (3u)

/** \brief Mask for Ifx_DOM_SCICTRL_PRIORITY_Bits.HPRS */
#define IFX_DOM_SCICTRL_PRIORITY_HPRS_MSK (0x7u)

/** \brief Offset for Ifx_DOM_SCICTRL_PRIORITY_Bits.HPRS */
#define IFX_DOM_SCICTRL_PRIORITY_HPRS_OFF (16u)

/** \brief Length for Ifx_DOM_SCICTRL_ERRADDR_Bits.ADDR */
#define IFX_DOM_SCICTRL_ERRADDR_ADDR_LEN (32u)

/** \brief Mask for Ifx_DOM_SCICTRL_ERRADDR_Bits.ADDR */
#define IFX_DOM_SCICTRL_ERRADDR_ADDR_MSK (0xffffffffu)

/** \brief Offset for Ifx_DOM_SCICTRL_ERRADDR_Bits.ADDR */
#define IFX_DOM_SCICTRL_ERRADDR_ADDR_OFF (0u)

/** \brief Length for Ifx_DOM_SCICTRL_ERR_Bits.RD_N */
#define IFX_DOM_SCICTRL_ERR_RD_N_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_ERR_Bits.RD_N */
#define IFX_DOM_SCICTRL_ERR_RD_N_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_ERR_Bits.RD_N */
#define IFX_DOM_SCICTRL_ERR_RD_N_OFF (0u)

/** \brief Length for Ifx_DOM_SCICTRL_ERR_Bits.WR_N */
#define IFX_DOM_SCICTRL_ERR_WR_N_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_ERR_Bits.WR_N */
#define IFX_DOM_SCICTRL_ERR_WR_N_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_ERR_Bits.WR_N */
#define IFX_DOM_SCICTRL_ERR_WR_N_OFF (1u)

/** \brief Length for Ifx_DOM_SCICTRL_ERR_Bits.SVM */
#define IFX_DOM_SCICTRL_ERR_SVM_LEN (1u)

/** \brief Mask for Ifx_DOM_SCICTRL_ERR_Bits.SVM */
#define IFX_DOM_SCICTRL_ERR_SVM_MSK (0x1u)

/** \brief Offset for Ifx_DOM_SCICTRL_ERR_Bits.SVM */
#define IFX_DOM_SCICTRL_ERR_SVM_OFF (2u)

/** \brief Length for Ifx_DOM_SCICTRL_ERR_Bits.OPC */
#define IFX_DOM_SCICTRL_ERR_OPC_LEN (4u)

/** \brief Mask for Ifx_DOM_SCICTRL_ERR_Bits.OPC */
#define IFX_DOM_SCICTRL_ERR_OPC_MSK (0xfu)

/** \brief Offset for Ifx_DOM_SCICTRL_ERR_Bits.OPC */
#define IFX_DOM_SCICTRL_ERR_OPC_OFF (4u)

/** \brief Length for Ifx_DOM_SCICTRL_ERR_Bits.TR_ID */
#define IFX_DOM_SCICTRL_ERR_TR_ID_LEN (8u)

/** \brief Mask for Ifx_DOM_SCICTRL_ERR_Bits.TR_ID */
#define IFX_DOM_SCICTRL_ERR_TR_ID_MSK (0xffu)

/** \brief Offset for Ifx_DOM_SCICTRL_ERR_Bits.TR_ID */
#define IFX_DOM_SCICTRL_ERR_TR_ID_OFF (8u)

/** \brief Length for Ifx_DOM_SCICTRL_ERR_Bits.ADDR_EDC */
#define IFX_DOM_SCICTRL_ERR_ADDR_EDC_LEN (8u)

/** \brief Mask for Ifx_DOM_SCICTRL_ERR_Bits.ADDR_EDC */
#define IFX_DOM_SCICTRL_ERR_ADDR_EDC_MSK (0xffu)

/** \brief Offset for Ifx_DOM_SCICTRL_ERR_Bits.ADDR_EDC */
#define IFX_DOM_SCICTRL_ERR_ADDR_EDC_OFF (16u)

/** \brief Length for Ifx_DOM_SCICTRL_ERR_Bits.MCI_SBS */
#define IFX_DOM_SCICTRL_ERR_MCI_SBS_LEN (8u)

/** \brief Mask for Ifx_DOM_SCICTRL_ERR_Bits.MCI_SBS */
#define IFX_DOM_SCICTRL_ERR_MCI_SBS_MSK (0xffu)

/** \brief Offset for Ifx_DOM_SCICTRL_ERR_Bits.MCI_SBS */
#define IFX_DOM_SCICTRL_ERR_MCI_SBS_OFF (24u)

/** \brief Length for Ifx_DOM_ID_Bits.MOD_REV */
#define IFX_DOM_ID_MOD_REV_LEN (8u)

/** \brief Mask for Ifx_DOM_ID_Bits.MOD_REV */
#define IFX_DOM_ID_MOD_REV_MSK (0xffu)

/** \brief Offset for Ifx_DOM_ID_Bits.MOD_REV */
#define IFX_DOM_ID_MOD_REV_OFF (0u)

/** \brief Length for Ifx_DOM_ID_Bits.MOD_TYPE */
#define IFX_DOM_ID_MOD_TYPE_LEN (8u)

/** \brief Mask for Ifx_DOM_ID_Bits.MOD_TYPE */
#define IFX_DOM_ID_MOD_TYPE_MSK (0xffu)

/** \brief Offset for Ifx_DOM_ID_Bits.MOD_TYPE */
#define IFX_DOM_ID_MOD_TYPE_OFF (8u)

/** \brief Length for Ifx_DOM_ID_Bits.MOD_NUMBER */
#define IFX_DOM_ID_MOD_NUMBER_LEN (16u)

/** \brief Mask for Ifx_DOM_ID_Bits.MOD_NUMBER */
#define IFX_DOM_ID_MOD_NUMBER_MSK (0xffffu)

/** \brief Offset for Ifx_DOM_ID_Bits.MOD_NUMBER */
#define IFX_DOM_ID_MOD_NUMBER_OFF (16u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI0 */
#define IFX_DOM_PESTAT_PESCI0_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI0 */
#define IFX_DOM_PESTAT_PESCI0_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI0 */
#define IFX_DOM_PESTAT_PESCI0_OFF (16u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI1 */
#define IFX_DOM_PESTAT_PESCI1_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI1 */
#define IFX_DOM_PESTAT_PESCI1_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI1 */
#define IFX_DOM_PESTAT_PESCI1_OFF (17u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI2 */
#define IFX_DOM_PESTAT_PESCI2_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI2 */
#define IFX_DOM_PESTAT_PESCI2_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI2 */
#define IFX_DOM_PESTAT_PESCI2_OFF (18u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI3 */
#define IFX_DOM_PESTAT_PESCI3_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI3 */
#define IFX_DOM_PESTAT_PESCI3_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI3 */
#define IFX_DOM_PESTAT_PESCI3_OFF (19u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI4 */
#define IFX_DOM_PESTAT_PESCI4_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI4 */
#define IFX_DOM_PESTAT_PESCI4_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI4 */
#define IFX_DOM_PESTAT_PESCI4_OFF (20u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI5 */
#define IFX_DOM_PESTAT_PESCI5_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI5 */
#define IFX_DOM_PESTAT_PESCI5_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI5 */
#define IFX_DOM_PESTAT_PESCI5_OFF (21u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI6 */
#define IFX_DOM_PESTAT_PESCI6_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI6 */
#define IFX_DOM_PESTAT_PESCI6_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI6 */
#define IFX_DOM_PESTAT_PESCI6_OFF (22u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI7 */
#define IFX_DOM_PESTAT_PESCI7_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI7 */
#define IFX_DOM_PESTAT_PESCI7_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI7 */
#define IFX_DOM_PESTAT_PESCI7_OFF (23u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI8 */
#define IFX_DOM_PESTAT_PESCI8_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI8 */
#define IFX_DOM_PESTAT_PESCI8_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI8 */
#define IFX_DOM_PESTAT_PESCI8_OFF (24u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI9 */
#define IFX_DOM_PESTAT_PESCI9_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI9 */
#define IFX_DOM_PESTAT_PESCI9_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI9 */
#define IFX_DOM_PESTAT_PESCI9_OFF (25u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI10 */
#define IFX_DOM_PESTAT_PESCI10_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI10 */
#define IFX_DOM_PESTAT_PESCI10_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI10 */
#define IFX_DOM_PESTAT_PESCI10_OFF (26u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI11 */
#define IFX_DOM_PESTAT_PESCI11_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI11 */
#define IFX_DOM_PESTAT_PESCI11_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI11 */
#define IFX_DOM_PESTAT_PESCI11_OFF (27u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI12 */
#define IFX_DOM_PESTAT_PESCI12_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI12 */
#define IFX_DOM_PESTAT_PESCI12_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI12 */
#define IFX_DOM_PESTAT_PESCI12_OFF (28u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI13 */
#define IFX_DOM_PESTAT_PESCI13_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI13 */
#define IFX_DOM_PESTAT_PESCI13_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI13 */
#define IFX_DOM_PESTAT_PESCI13_OFF (29u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI14 */
#define IFX_DOM_PESTAT_PESCI14_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI14 */
#define IFX_DOM_PESTAT_PESCI14_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI14 */
#define IFX_DOM_PESTAT_PESCI14_OFF (30u)

/** \brief Length for Ifx_DOM_PESTAT_Bits.PESCI15 */
#define IFX_DOM_PESTAT_PESCI15_LEN (1u)

/** \brief Mask for Ifx_DOM_PESTAT_Bits.PESCI15 */
#define IFX_DOM_PESTAT_PESCI15_MSK (0x1u)

/** \brief Offset for Ifx_DOM_PESTAT_Bits.PESCI15 */
#define IFX_DOM_PESTAT_PESCI15_OFF (31u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI0 */
#define IFX_DOM_TIDSTAT_TIDSCI0_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI0 */
#define IFX_DOM_TIDSTAT_TIDSCI0_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI0 */
#define IFX_DOM_TIDSTAT_TIDSCI0_OFF (0u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI1 */
#define IFX_DOM_TIDSTAT_TIDSCI1_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI1 */
#define IFX_DOM_TIDSTAT_TIDSCI1_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI1 */
#define IFX_DOM_TIDSTAT_TIDSCI1_OFF (1u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI2 */
#define IFX_DOM_TIDSTAT_TIDSCI2_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI2 */
#define IFX_DOM_TIDSTAT_TIDSCI2_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI2 */
#define IFX_DOM_TIDSTAT_TIDSCI2_OFF (2u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI3 */
#define IFX_DOM_TIDSTAT_TIDSCI3_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI3 */
#define IFX_DOM_TIDSTAT_TIDSCI3_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI3 */
#define IFX_DOM_TIDSTAT_TIDSCI3_OFF (3u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI4 */
#define IFX_DOM_TIDSTAT_TIDSCI4_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI4 */
#define IFX_DOM_TIDSTAT_TIDSCI4_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI4 */
#define IFX_DOM_TIDSTAT_TIDSCI4_OFF (4u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI5 */
#define IFX_DOM_TIDSTAT_TIDSCI5_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI5 */
#define IFX_DOM_TIDSTAT_TIDSCI5_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI5 */
#define IFX_DOM_TIDSTAT_TIDSCI5_OFF (5u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI6 */
#define IFX_DOM_TIDSTAT_TIDSCI6_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI6 */
#define IFX_DOM_TIDSTAT_TIDSCI6_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI6 */
#define IFX_DOM_TIDSTAT_TIDSCI6_OFF (6u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI7 */
#define IFX_DOM_TIDSTAT_TIDSCI7_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI7 */
#define IFX_DOM_TIDSTAT_TIDSCI7_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI7 */
#define IFX_DOM_TIDSTAT_TIDSCI7_OFF (7u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI8 */
#define IFX_DOM_TIDSTAT_TIDSCI8_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI8 */
#define IFX_DOM_TIDSTAT_TIDSCI8_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI8 */
#define IFX_DOM_TIDSTAT_TIDSCI8_OFF (8u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI9 */
#define IFX_DOM_TIDSTAT_TIDSCI9_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI9 */
#define IFX_DOM_TIDSTAT_TIDSCI9_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI9 */
#define IFX_DOM_TIDSTAT_TIDSCI9_OFF (9u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI10 */
#define IFX_DOM_TIDSTAT_TIDSCI10_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI10 */
#define IFX_DOM_TIDSTAT_TIDSCI10_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI10 */
#define IFX_DOM_TIDSTAT_TIDSCI10_OFF (10u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI11 */
#define IFX_DOM_TIDSTAT_TIDSCI11_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI11 */
#define IFX_DOM_TIDSTAT_TIDSCI11_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI11 */
#define IFX_DOM_TIDSTAT_TIDSCI11_OFF (11u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI12 */
#define IFX_DOM_TIDSTAT_TIDSCI12_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI12 */
#define IFX_DOM_TIDSTAT_TIDSCI12_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI12 */
#define IFX_DOM_TIDSTAT_TIDSCI12_OFF (12u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI13 */
#define IFX_DOM_TIDSTAT_TIDSCI13_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI13 */
#define IFX_DOM_TIDSTAT_TIDSCI13_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI13 */
#define IFX_DOM_TIDSTAT_TIDSCI13_OFF (13u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI14 */
#define IFX_DOM_TIDSTAT_TIDSCI14_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI14 */
#define IFX_DOM_TIDSTAT_TIDSCI14_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI14 */
#define IFX_DOM_TIDSTAT_TIDSCI14_OFF (14u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDSCI15 */
#define IFX_DOM_TIDSTAT_TIDSCI15_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDSCI15 */
#define IFX_DOM_TIDSTAT_TIDSCI15_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDSCI15 */
#define IFX_DOM_TIDSTAT_TIDSCI15_OFF (15u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI0 */
#define IFX_DOM_TIDSTAT_TIDMCI0_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI0 */
#define IFX_DOM_TIDSTAT_TIDMCI0_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI0 */
#define IFX_DOM_TIDSTAT_TIDMCI0_OFF (16u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI1 */
#define IFX_DOM_TIDSTAT_TIDMCI1_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI1 */
#define IFX_DOM_TIDSTAT_TIDMCI1_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI1 */
#define IFX_DOM_TIDSTAT_TIDMCI1_OFF (17u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI2 */
#define IFX_DOM_TIDSTAT_TIDMCI2_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI2 */
#define IFX_DOM_TIDSTAT_TIDMCI2_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI2 */
#define IFX_DOM_TIDSTAT_TIDMCI2_OFF (18u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI3 */
#define IFX_DOM_TIDSTAT_TIDMCI3_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI3 */
#define IFX_DOM_TIDSTAT_TIDMCI3_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI3 */
#define IFX_DOM_TIDSTAT_TIDMCI3_OFF (19u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI4 */
#define IFX_DOM_TIDSTAT_TIDMCI4_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI4 */
#define IFX_DOM_TIDSTAT_TIDMCI4_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI4 */
#define IFX_DOM_TIDSTAT_TIDMCI4_OFF (20u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI5 */
#define IFX_DOM_TIDSTAT_TIDMCI5_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI5 */
#define IFX_DOM_TIDSTAT_TIDMCI5_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI5 */
#define IFX_DOM_TIDSTAT_TIDMCI5_OFF (21u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI6 */
#define IFX_DOM_TIDSTAT_TIDMCI6_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI6 */
#define IFX_DOM_TIDSTAT_TIDMCI6_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI6 */
#define IFX_DOM_TIDSTAT_TIDMCI6_OFF (22u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI7 */
#define IFX_DOM_TIDSTAT_TIDMCI7_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI7 */
#define IFX_DOM_TIDSTAT_TIDMCI7_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI7 */
#define IFX_DOM_TIDSTAT_TIDMCI7_OFF (23u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI8 */
#define IFX_DOM_TIDSTAT_TIDMCI8_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI8 */
#define IFX_DOM_TIDSTAT_TIDMCI8_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI8 */
#define IFX_DOM_TIDSTAT_TIDMCI8_OFF (24u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI9 */
#define IFX_DOM_TIDSTAT_TIDMCI9_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI9 */
#define IFX_DOM_TIDSTAT_TIDMCI9_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI9 */
#define IFX_DOM_TIDSTAT_TIDMCI9_OFF (25u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI10 */
#define IFX_DOM_TIDSTAT_TIDMCI10_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI10 */
#define IFX_DOM_TIDSTAT_TIDMCI10_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI10 */
#define IFX_DOM_TIDSTAT_TIDMCI10_OFF (26u)

/** \brief Length for Ifx_DOM_TIDSTAT_Bits.TIDMCI11 */
#define IFX_DOM_TIDSTAT_TIDMCI11_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDSTAT_Bits.TIDMCI11 */
#define IFX_DOM_TIDSTAT_TIDMCI11_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDSTAT_Bits.TIDMCI11 */
#define IFX_DOM_TIDSTAT_TIDMCI11_OFF (27u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI0 */
#define IFX_DOM_TIDEN_ENSCI0_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI0 */
#define IFX_DOM_TIDEN_ENSCI0_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI0 */
#define IFX_DOM_TIDEN_ENSCI0_OFF (0u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI1 */
#define IFX_DOM_TIDEN_ENSCI1_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI1 */
#define IFX_DOM_TIDEN_ENSCI1_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI1 */
#define IFX_DOM_TIDEN_ENSCI1_OFF (1u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI2 */
#define IFX_DOM_TIDEN_ENSCI2_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI2 */
#define IFX_DOM_TIDEN_ENSCI2_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI2 */
#define IFX_DOM_TIDEN_ENSCI2_OFF (2u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI3 */
#define IFX_DOM_TIDEN_ENSCI3_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI3 */
#define IFX_DOM_TIDEN_ENSCI3_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI3 */
#define IFX_DOM_TIDEN_ENSCI3_OFF (3u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI4 */
#define IFX_DOM_TIDEN_ENSCI4_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI4 */
#define IFX_DOM_TIDEN_ENSCI4_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI4 */
#define IFX_DOM_TIDEN_ENSCI4_OFF (4u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI5 */
#define IFX_DOM_TIDEN_ENSCI5_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI5 */
#define IFX_DOM_TIDEN_ENSCI5_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI5 */
#define IFX_DOM_TIDEN_ENSCI5_OFF (5u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI6 */
#define IFX_DOM_TIDEN_ENSCI6_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI6 */
#define IFX_DOM_TIDEN_ENSCI6_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI6 */
#define IFX_DOM_TIDEN_ENSCI6_OFF (6u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI7 */
#define IFX_DOM_TIDEN_ENSCI7_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI7 */
#define IFX_DOM_TIDEN_ENSCI7_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI7 */
#define IFX_DOM_TIDEN_ENSCI7_OFF (7u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI8 */
#define IFX_DOM_TIDEN_ENSCI8_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI8 */
#define IFX_DOM_TIDEN_ENSCI8_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI8 */
#define IFX_DOM_TIDEN_ENSCI8_OFF (8u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI9 */
#define IFX_DOM_TIDEN_ENSCI9_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI9 */
#define IFX_DOM_TIDEN_ENSCI9_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI9 */
#define IFX_DOM_TIDEN_ENSCI9_OFF (9u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI10 */
#define IFX_DOM_TIDEN_ENSCI10_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI10 */
#define IFX_DOM_TIDEN_ENSCI10_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI10 */
#define IFX_DOM_TIDEN_ENSCI10_OFF (10u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI11 */
#define IFX_DOM_TIDEN_ENSCI11_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI11 */
#define IFX_DOM_TIDEN_ENSCI11_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI11 */
#define IFX_DOM_TIDEN_ENSCI11_OFF (11u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI12 */
#define IFX_DOM_TIDEN_ENSCI12_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI12 */
#define IFX_DOM_TIDEN_ENSCI12_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI12 */
#define IFX_DOM_TIDEN_ENSCI12_OFF (12u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI13 */
#define IFX_DOM_TIDEN_ENSCI13_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI13 */
#define IFX_DOM_TIDEN_ENSCI13_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI13 */
#define IFX_DOM_TIDEN_ENSCI13_OFF (13u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI14 */
#define IFX_DOM_TIDEN_ENSCI14_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI14 */
#define IFX_DOM_TIDEN_ENSCI14_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI14 */
#define IFX_DOM_TIDEN_ENSCI14_OFF (14u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENSCI15 */
#define IFX_DOM_TIDEN_ENSCI15_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENSCI15 */
#define IFX_DOM_TIDEN_ENSCI15_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENSCI15 */
#define IFX_DOM_TIDEN_ENSCI15_OFF (15u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI0 */
#define IFX_DOM_TIDEN_ENMCI0_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI0 */
#define IFX_DOM_TIDEN_ENMCI0_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI0 */
#define IFX_DOM_TIDEN_ENMCI0_OFF (16u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI1 */
#define IFX_DOM_TIDEN_ENMCI1_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI1 */
#define IFX_DOM_TIDEN_ENMCI1_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI1 */
#define IFX_DOM_TIDEN_ENMCI1_OFF (17u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI2 */
#define IFX_DOM_TIDEN_ENMCI2_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI2 */
#define IFX_DOM_TIDEN_ENMCI2_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI2 */
#define IFX_DOM_TIDEN_ENMCI2_OFF (18u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI3 */
#define IFX_DOM_TIDEN_ENMCI3_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI3 */
#define IFX_DOM_TIDEN_ENMCI3_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI3 */
#define IFX_DOM_TIDEN_ENMCI3_OFF (19u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI4 */
#define IFX_DOM_TIDEN_ENMCI4_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI4 */
#define IFX_DOM_TIDEN_ENMCI4_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI4 */
#define IFX_DOM_TIDEN_ENMCI4_OFF (20u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI5 */
#define IFX_DOM_TIDEN_ENMCI5_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI5 */
#define IFX_DOM_TIDEN_ENMCI5_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI5 */
#define IFX_DOM_TIDEN_ENMCI5_OFF (21u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI6 */
#define IFX_DOM_TIDEN_ENMCI6_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI6 */
#define IFX_DOM_TIDEN_ENMCI6_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI6 */
#define IFX_DOM_TIDEN_ENMCI6_OFF (22u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI7 */
#define IFX_DOM_TIDEN_ENMCI7_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI7 */
#define IFX_DOM_TIDEN_ENMCI7_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI7 */
#define IFX_DOM_TIDEN_ENMCI7_OFF (23u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI8 */
#define IFX_DOM_TIDEN_ENMCI8_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI8 */
#define IFX_DOM_TIDEN_ENMCI8_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI8 */
#define IFX_DOM_TIDEN_ENMCI8_OFF (24u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI9 */
#define IFX_DOM_TIDEN_ENMCI9_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI9 */
#define IFX_DOM_TIDEN_ENMCI9_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI9 */
#define IFX_DOM_TIDEN_ENMCI9_OFF (25u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI10 */
#define IFX_DOM_TIDEN_ENMCI10_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI10 */
#define IFX_DOM_TIDEN_ENMCI10_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI10 */
#define IFX_DOM_TIDEN_ENMCI10_OFF (26u)

/** \brief Length for Ifx_DOM_TIDEN_Bits.ENMCI11 */
#define IFX_DOM_TIDEN_ENMCI11_LEN (1u)

/** \brief Mask for Ifx_DOM_TIDEN_Bits.ENMCI11 */
#define IFX_DOM_TIDEN_ENMCI11_MSK (0x1u)

/** \brief Offset for Ifx_DOM_TIDEN_Bits.ENMCI11 */
#define IFX_DOM_TIDEN_ENMCI11_OFF (27u)

/** \brief Length for Ifx_DOM_BRCON_Bits.OLDAEN */
#define IFX_DOM_BRCON_OLDAEN_LEN (1u)

/** \brief Mask for Ifx_DOM_BRCON_Bits.OLDAEN */
#define IFX_DOM_BRCON_OLDAEN_MSK (0x1u)

/** \brief Offset for Ifx_DOM_BRCON_Bits.OLDAEN */
#define IFX_DOM_BRCON_OLDAEN_OFF (0u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN0 */
#define IFX_DOM_ACCEN0_EN0_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN0 */
#define IFX_DOM_ACCEN0_EN0_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN0 */
#define IFX_DOM_ACCEN0_EN0_OFF (0u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN1 */
#define IFX_DOM_ACCEN0_EN1_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN1 */
#define IFX_DOM_ACCEN0_EN1_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN1 */
#define IFX_DOM_ACCEN0_EN1_OFF (1u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN2 */
#define IFX_DOM_ACCEN0_EN2_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN2 */
#define IFX_DOM_ACCEN0_EN2_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN2 */
#define IFX_DOM_ACCEN0_EN2_OFF (2u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN3 */
#define IFX_DOM_ACCEN0_EN3_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN3 */
#define IFX_DOM_ACCEN0_EN3_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN3 */
#define IFX_DOM_ACCEN0_EN3_OFF (3u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN4 */
#define IFX_DOM_ACCEN0_EN4_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN4 */
#define IFX_DOM_ACCEN0_EN4_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN4 */
#define IFX_DOM_ACCEN0_EN4_OFF (4u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN5 */
#define IFX_DOM_ACCEN0_EN5_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN5 */
#define IFX_DOM_ACCEN0_EN5_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN5 */
#define IFX_DOM_ACCEN0_EN5_OFF (5u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN6 */
#define IFX_DOM_ACCEN0_EN6_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN6 */
#define IFX_DOM_ACCEN0_EN6_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN6 */
#define IFX_DOM_ACCEN0_EN6_OFF (6u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN7 */
#define IFX_DOM_ACCEN0_EN7_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN7 */
#define IFX_DOM_ACCEN0_EN7_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN7 */
#define IFX_DOM_ACCEN0_EN7_OFF (7u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN8 */
#define IFX_DOM_ACCEN0_EN8_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN8 */
#define IFX_DOM_ACCEN0_EN8_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN8 */
#define IFX_DOM_ACCEN0_EN8_OFF (8u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN9 */
#define IFX_DOM_ACCEN0_EN9_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN9 */
#define IFX_DOM_ACCEN0_EN9_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN9 */
#define IFX_DOM_ACCEN0_EN9_OFF (9u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN10 */
#define IFX_DOM_ACCEN0_EN10_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN10 */
#define IFX_DOM_ACCEN0_EN10_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN10 */
#define IFX_DOM_ACCEN0_EN10_OFF (10u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN11 */
#define IFX_DOM_ACCEN0_EN11_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN11 */
#define IFX_DOM_ACCEN0_EN11_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN11 */
#define IFX_DOM_ACCEN0_EN11_OFF (11u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN12 */
#define IFX_DOM_ACCEN0_EN12_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN12 */
#define IFX_DOM_ACCEN0_EN12_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN12 */
#define IFX_DOM_ACCEN0_EN12_OFF (12u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN13 */
#define IFX_DOM_ACCEN0_EN13_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN13 */
#define IFX_DOM_ACCEN0_EN13_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN13 */
#define IFX_DOM_ACCEN0_EN13_OFF (13u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN14 */
#define IFX_DOM_ACCEN0_EN14_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN14 */
#define IFX_DOM_ACCEN0_EN14_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN14 */
#define IFX_DOM_ACCEN0_EN14_OFF (14u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN15 */
#define IFX_DOM_ACCEN0_EN15_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN15 */
#define IFX_DOM_ACCEN0_EN15_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN15 */
#define IFX_DOM_ACCEN0_EN15_OFF (15u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN16 */
#define IFX_DOM_ACCEN0_EN16_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN16 */
#define IFX_DOM_ACCEN0_EN16_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN16 */
#define IFX_DOM_ACCEN0_EN16_OFF (16u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN17 */
#define IFX_DOM_ACCEN0_EN17_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN17 */
#define IFX_DOM_ACCEN0_EN17_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN17 */
#define IFX_DOM_ACCEN0_EN17_OFF (17u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN18 */
#define IFX_DOM_ACCEN0_EN18_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN18 */
#define IFX_DOM_ACCEN0_EN18_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN18 */
#define IFX_DOM_ACCEN0_EN18_OFF (18u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN19 */
#define IFX_DOM_ACCEN0_EN19_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN19 */
#define IFX_DOM_ACCEN0_EN19_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN19 */
#define IFX_DOM_ACCEN0_EN19_OFF (19u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN20 */
#define IFX_DOM_ACCEN0_EN20_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN20 */
#define IFX_DOM_ACCEN0_EN20_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN20 */
#define IFX_DOM_ACCEN0_EN20_OFF (20u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN21 */
#define IFX_DOM_ACCEN0_EN21_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN21 */
#define IFX_DOM_ACCEN0_EN21_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN21 */
#define IFX_DOM_ACCEN0_EN21_OFF (21u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN22 */
#define IFX_DOM_ACCEN0_EN22_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN22 */
#define IFX_DOM_ACCEN0_EN22_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN22 */
#define IFX_DOM_ACCEN0_EN22_OFF (22u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN23 */
#define IFX_DOM_ACCEN0_EN23_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN23 */
#define IFX_DOM_ACCEN0_EN23_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN23 */
#define IFX_DOM_ACCEN0_EN23_OFF (23u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN24 */
#define IFX_DOM_ACCEN0_EN24_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN24 */
#define IFX_DOM_ACCEN0_EN24_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN24 */
#define IFX_DOM_ACCEN0_EN24_OFF (24u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN25 */
#define IFX_DOM_ACCEN0_EN25_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN25 */
#define IFX_DOM_ACCEN0_EN25_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN25 */
#define IFX_DOM_ACCEN0_EN25_OFF (25u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN26 */
#define IFX_DOM_ACCEN0_EN26_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN26 */
#define IFX_DOM_ACCEN0_EN26_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN26 */
#define IFX_DOM_ACCEN0_EN26_OFF (26u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN27 */
#define IFX_DOM_ACCEN0_EN27_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN27 */
#define IFX_DOM_ACCEN0_EN27_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN27 */
#define IFX_DOM_ACCEN0_EN27_OFF (27u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN28 */
#define IFX_DOM_ACCEN0_EN28_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN28 */
#define IFX_DOM_ACCEN0_EN28_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN28 */
#define IFX_DOM_ACCEN0_EN28_OFF (28u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN29 */
#define IFX_DOM_ACCEN0_EN29_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN29 */
#define IFX_DOM_ACCEN0_EN29_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN29 */
#define IFX_DOM_ACCEN0_EN29_OFF (29u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN30 */
#define IFX_DOM_ACCEN0_EN30_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN30 */
#define IFX_DOM_ACCEN0_EN30_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN30 */
#define IFX_DOM_ACCEN0_EN30_OFF (30u)

/** \brief Length for Ifx_DOM_ACCEN0_Bits.EN31 */
#define IFX_DOM_ACCEN0_EN31_LEN (1u)

/** \brief Mask for Ifx_DOM_ACCEN0_Bits.EN31 */
#define IFX_DOM_ACCEN0_EN31_MSK (0x1u)

/** \brief Offset for Ifx_DOM_ACCEN0_Bits.EN31 */
#define IFX_DOM_ACCEN0_EN31_OFF (31u)

/** \}  */

/******************************************************************************/

/******************************************************************************/

#endif /* IFXDOM_BF_H */
